1. Field of Invention
The present invention generally relates to a comparator, and more particularly to a comparator which reduces oxide stress of an output power stage connected thereto.
2. Description of Prior Art
A comparator is widely used in the semiconductor circuit for various applications. The comparator may be used in the voltage regulator. The voltage regulator comprises a voltage divider circuit, a comparator, and a power MOS transistor. The power MOS transistor is an output power stage connected to the comparator, and controlled by a comparison result of the comparator to provide a voltage from a power voltage to the voltage divider circuit. The voltage divider circuit generates a dividing voltage based on the received voltage provided by the power MOS transistor. The comparator compares the dividing voltage and a reference voltage, and generates the comparison result to control the power MOS transistor, such that the voltage regulation can be achieved.
Referring to FIG. 1, FIG. 1 is a circuit diagram of a conventional comparator. The comparator 10 comprises a differential input pair IN_D_PAIR, a current mirror CM, and an enable switch 11. The comparator 10 compares an input voltages VP and VN, and correspondingly outputs the comparison result VOUT at an output node thereof. The enable switch 11 is not the essential element of the comparator 10, and may be removed in the other example.
The differential input pair IN_D_PAIR comprises NMOS transistors N1 and N2, wherein gates of the NMOS transistors N1, N2 are respectively connected to a positive input end and a negative input end of the comparator 10 for respectively receiving the input voltages VP and VN, and sources of the NMOS transistors N1, N2 are coupled to a ground through the enable switch 11.
The current mirror CM comprises PMOS transistors P1 and P2, wherein gates of the PMOS transistors P1 and P2 are connected together and the gates of the PMOS transistors P1 and P2 are coupled to the NMOS transistor N1. Moreover, the PMOS transistors P1 and P2 coupled to a power voltage VDD.
The enable switch 11 is a NMOS transistor N4, wherein a gate of the NMOS transistor N4 is coupled to a control signal VBIAS, a drain of the NMOS transistor N4 is coupled to the sources of the NMOS transistors N1, N2, and a source of the NMOS transistor N4 is coupled to the ground. The comparator 10 is turned on when the enable switch 11 is controlled to be short, and the comparator 10 is turned off when the enable switch 11 is controlled to be open, such that the current consumption can be saved when the comparator 10 is not desired to be used.
Please notice here, range of the comparison result VOur in the above example is from 0V through VDD (i.e. 0≦VOUT≦VDD), and thus the output power stage must endure the power voltage VDD. Regarding the semiconductor process of 3.3V, the power voltage may be 3.6V, and an allowed pass current is specified to be 55 A. Thus the oxide stress of the output power stage is 3.6V/55 A=6.5 MegV/cm, which excesses the specified maximum oxide stress of the semiconductor process of 3.3V, and thus the oxide thickness should be increased via modifying the optical mask during the semiconductor process of 3.3V. However, modifying the optical mask during the semiconductor process of 3.3V causes large mount of extra cost, and this method for preventing the MOS transistor from burning out is not economically. Therefore, designing a comparator for preventing the MOS transistor from burning out without modifying the optical mask is needed.